1. Field of the Invention
The invention relates to a circuit arrangement of multiplexers, that is a bus circuit of multiplexers for connecting transceiver circuits with connecting lines for outputting and receiving a data signal and a control signal that characterizes a data signal.
The circuit described herein is to be used, in particular, to connect a number of transceiver circuits to one another in such a manner that they are capable of communicating with one another. This task is frequently handled by so-called tristate buses but these have some disadvantages. Thus, the capacitive loading on the bus line—caused by disconnected transmit circuits of the bus users—is proportional to the transmit power of the transmitting bus user. The ratio between transmit power and capacitive loading can not, therefore, be improved selectively by design measures but depends on technology parameters and the number of transceiver circuits involved. With a given technology, the transmission speed, which can be achieved is thus a function of the number of connected transceiver circuits alone. In particular, the transmission speed is reduced with increased numbers of bus users.
Furthermore, the use of a tristate bus requires relatively elaborate drive logic. Since the simultaneous transmission by two bus users would be equivalent to a short circuit, it must be ensured that two transceiver circuits never simultaneously place a signal on the bus. When switching from one transceiver circuit to the other one, a pause must be inserted in each case wherein no bus user at all is active and this pause must be synchronized via a central clock. The problem arises especially in the case of complex bus systems that it is no longer possible to ensure that the clock signals are simultaneously received by all transceiver circuits. Thus, the pause must be correspondingly large enough to ensure that no two bus users are transmitting at the same time even with such delay differences of clock signals. Furthermore, the dimensioning and verification in the development of tristate buses is only very inadequately supported by currently available CAD tools.
To avoid disadvantages of this type, multiplexers are also used instead of tristate buses. In principle, two equivalent solutions to the problem are known. In the first case, each transceiver circuit is given its own multiplexer at its input by means of which it can determine from which transceiver circuit it wishes to receive signals. In the second case, each transceiver circuit sends its signal to a centrally arranged distributor circuit, which selects one of the incoming signals and forwards it to all connected transceiver circuits.
These two possibilities also provide some problems. In particular, the two solutions do not occupy optimum areas but need a relatively large spatial area since a great number of connecting lines must be run between the individual transceiver circuits and the associated multiplexers. The space requirement often exceeds that of an equivalent tristate bus by a multiple. Furthermore, a given structure is restricted to a certain number of transceiver circuits and can thus not be expanded very flexibly. If another bus user is to be added, the entire structure of the connecting lines must be adapted to this new situation.